FIG. 1 illustrates a conventional bipolar junction transistor 10. The device is formed on a silicon substrate which is illustratively P.sup.- type. A buried N.sup.+ layer 14 is located on the substrate 12. An N-type collector region 16 is located on the buried N.sup.+ layer 14. A plurality of field oxide (FOX) regions 18 are formed on the substrate. An N.sup.+ deep connection region 20 connects the substrate surface to the buried N.sup.+ layer 14 to form a collector contact for contacting the collector 16. A P-type base region 22 is formed in the N-type well 16, which well forms the collector. Two P.sup.+ -type base contact regions 24 and 26 are formed on either side of the base 22. The emitter 28 includes the N.sup.+ polysilicon or polycide region 30 formed on the surface of the substrate. The emitter 28 also includes the N.sup.+ region 29. Spacers such as oxide spacers 32 and 34 are located on either side of the polysilicon region 30. Two metal contacts 36 and 38 connect to the P.sup.+ base contact regions 24 and 26. A third metal contact 40 connects to the deep connector region 20 for contact with the N.sup.+ collector contact layer 14. The metal contacts 36, 38 and 40 are formed in openings of a metal-poly-dielectric (MPD) layer 42.
The overall structure is an NPN transistor with N-type collector 16, P-type base 22 and N-type emitter 28. The buried N.sup.+ layer 14 and N.sup.+ deep connector 20 form a collector contact. The P.sup.+ regions 24 and 26 form a base contact.
It should be noted that in the conventional bipolar junction transistor (BJT) shown in FIG. 1, the P.sup.+ base contact regions 24 and 26 are large (e.g. a depth of 0.3 .mu.m and a width of 1.4 .mu.m). Hence, there is a large base to collector capacitance that degrades BJT performance greatly. (The base contact regions 24 and 26 are large because it is necessary to account for base contact to emitter and base contact to FOX edge misalignment.)
To improve the BJT characteristics the BJT is formed using a process so that the base contact is self-aligned. A BJT 10' with a self-aligned base contact is illustrated in FIG. 2 and is formed as follows. Using conventional front end processes, the N.sup.+ layer 14 is formed on the substrate 12. The N-type collector region 16 is formed and then the field oxide (FOX) regions 18 are formed on the substrate surface. The deep collector connector region 20 is then formed by diffusion or ion implantations into the N-well 16. Next, the P base region 22 is formed by diffusion or ion implantation. Next the P.sup.+ polysilicon interconnect links 54 and 56 are formed. The interconnect links 54 and 56 are formed by depositing a polysilicon layer, patterning the polysilicon layer using photolithography and then etching. The P.sup.+ base contact regions 24 and 26 are formed by out-diffusion from the P.sup.+ polysilicon interconnect links 54 and 56. This forms a self-aligned link from the P base 22, through the P.sup.+ base contact regions 24 and 26, and through the P.sup.+ polysilicon regions 54 and 56 to the base metal contacts 36 and 38 (which are formed after MPD deposition).
Next the inter emitter base isolation oxide regions 64 and 66 are formed by depositing an oxide layer and patterning the oxide layer. Then the emitter 28 is formed by depositing a N.sup.+ polysilicon layer and patterning this layer to form the N.sup.+ polysilicon emitter region 30. The N.sup.+ emitter region 29 is formed by out-diffusion from the N.sup.+ polysilicon region 30. After this, the MPD layer 42 is formed and patterned to enable formation of the metal contacts 36, 38 and 40.
From these steps the BJT 10' with the self aligned base contact is formed. Because the P base 22 is connected using the P.sup.+ polysilicon regions 54 and 56, the P.sup.+ base contact regions 24 and 26 can be made smaller than in the conventional device of FIG. 1. Thus, the collector-base capacitance in the device 10' of FIG. 2 is smaller than in the device 10 of FIG. 1.
However, the device 10' of FIG. 2 still has certain deficiencies. First of all, the P.sup.+ base contact regions 24 and 26 are formed before a thermal cycle is used to form the N.sup.+ emitter region 29 by out-diffusion from the N.sup.+ polysilicon region 30. This thermal cycle will cause the P.sup.+ impurities in the P.sup.+ regions 24 and 26 to out-diffuse, thereby enlarging the size of the P.sup.+ regions 24 and 26. This in turn can cause N.sup.+ emitter region (region 29) to P.sup.+ base contact region (regions 24 and 26) junction leakage. In addition, the base to collector capacitance will be increased. Moreover, because the P.sup.+ base contact regions 24 and 26 are formed by out-diffusion from the P.sup.+ links 54 and 56, only polysilicon or polycide can be used for these links and this results in a large base interconnection resistance.
It is an object of the invention to provide a process for forming BJT with a self aligned base contact which overcomes the problems of the conventional BJT with self-aligned base contact.